vunit
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VUnit
VUnit is a unit testing framework for VHDL/SystemVerilog
Like `icarus verilog`
Avoid undefined signals on outgoing ports of the ram interface.
The documentation of the add_source_files method should be improved to reflect that you can pass iterables like sets and lists of file names. An example could also be added for...
This PR contains a bunch of changes that I missed. - Have it in the context, just for usability - Allow to disable the monitoring. We have lots of error...
The VUnit library offers great methods of compiling a project and dealing with test benches. Currently, I'm looking for a solution to offer fast compilation feedback in merge/pull requests. I...
Is it possible to have a feature to control execution order of the testbenches? Like having short testbenches executed first and then slow ones last or something similar.
Here is the problem: $ make compile Traceback (most recent call last): File "C:\My_Designs\probe_fpga_design_1\run.py", line 336, in main() File "C:\My_Designs\probe_fpga_design_1\run.py", line 181, in main vu.add_osvvm() File "c:\my_designs\probe_fpga_design_1\deps\vunit\vunit\ui\__init__.py", line 1030, in...
When a simulator runs in GUI mode, the following procedures are expected to be available from the GUI console window: ``` # vunit_help # - Prints this help # vunit_load...
Hi, WHen generating a Xilinx ROM IP (Vivado), I can fill the memeory contents with a COE-file. THe resulting simulation outout generates a MIF-file, In a stand-alone simulation this MIF...
The pattern matching in `ui.library.get_test_benches()` behaves slightly different on Window and Linux. When I give it the exact name of a test bench without leading wildcards, it does not find...
