vunit icon indicating copy to clipboard operation
vunit copied to clipboard

VUnit is a unit testing framework for VHDL/SystemVerilog

Results 231 vunit issues
Sort by recently updated
recently updated
newest added

This PR is built on top of #509. It will be kept as a draft until #509 is merged, at least. Coming from #480, this PR is related to: -...

Verification Components

**This PR is an example of how users can use GHDL + VUnit + VHPIDIRECT without built-in types. For practical cases, using `string_ptr`, `byte_vector_ptr` and/or `integer_vector_ptr` instead is recommended. See...

CoSim

**NOT READY FOR MERGE** Ref #465. Close #462. This PR allows to use `integer_vector_access_t` (memory buffers) defined in external C functions, along with the default internal model. The API for...

CoSim

A common scenario when developing is that once you update a block you would want to run the simulation of that block and all blocks that are dependent on it....

This is a simple counter-part of the signal_checker / std_logic_checker.

#614 was unwantedly closed while reorganising the branches in the repo. /cc @LarsAsplund @GlenNicholls

The first issue I encounter is because of line 138 of file vunit_pkg.sv, when I launch a test it doesn't end. I had to replace the $stop by $finish (Running...

Simulator support
SystemVerilog

Hello, I am trying to simulate a larger top level design (entire Series-7 FPGA), featuring several transceiver-based IPs. So far, I have been able to simulate this design when not...

The core development team for VUnit does not have easy access to Cadence Incisive and Xcelium licenses which prevents us from running our acceptance tests on those simulators. To get...

Help wanted
Simulator support

Hi, I find myself using Vunits avalon verification components quite often - mostly for simple register interfaces etc. and the full burst interface stuff seems to be a bit overkill...

Enhancement
Verification Components