compiling verilog code in verilator by Verilator 4.216 2021-12-05 rev v4.216

[SoCScholar]

while compiling verilog code ( .v), i get following errors.. can you please tell me where is error either of generated code from scala to verilog (by sbt "runMain vexriscv.demo.Murax" )

or of verilator ? ( verilator --Wall --cc VexRiscv.v)

:/opt/himal/VexRiscv$ verilator --cc VexRiscv.v

:/opt/himal/VexRiscv$ verilator --Wall --cc VexRiscv.v

as Verilator found a mismatch in the number of bits between the left-hand side (LHS) and right-hand side (RHS)

%Warning-WIDTH: VexRiscv.v:1673:55: Operator ASSIGNW expects 30 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. : ... In instance VexRiscv 1673 | assign _zz__zz_decode_PREDICTION_CONTEXT_hazard_4_1 = (IBusCachedPlugin_iBusRsp_stages_0_input_payload >>> 2'd2); | ^ ... For warning description see https://verilator.org/warn/WIDTH?v=4.216 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: VexRiscv.v:1683:44: Operator ASSIGNW expects 27 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. : ... In instance VexRiscv 1683 | assign _zz_io_cpu_flush_payload_lineId_1 = (execute_RS1 >>> 3'd5); | ^ %Warning-WIDTH: VexRiscv.v:3688:53: Operator ASSIGNW expects 30 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. : ... In instance VexRiscv 3688 | assign _zz_decode_PREDICTION_CONTEXT_line_history = (IBusCachedPlugin_fetchPc_output_payload >>> 2'd2); | ^ %Error: Exiting due to 3 warning(s)