Data Stream in/out SoC <-> FPGA

[lk-davidegironi]

Hello,

I'm building a softcore based on Briey. I've the AxiCrossbar without Sdram and on the APB3Bridge 1 Timer, 1 UartCtrl, 1 Gpio. On the APB3 I would like to add a custom Ctrl to transfer in and output data stream. I've to transfer 32x24bit data in + 32x16bit data output, and do some simple (for now) math inside the SoC on that stream.

I've try setting a Vector of Bits and now I'm trying Axi4Stream, based on that code here: https://github.com/SpinalHDL/VexRiscv/pull/53 In both options (Vector and Axi4Stream), I've a couple of issue, before moving to issues, I would like to ask you which could be a good option.

As far as I understand using Vec means using more LUT cause all the signals have to be synthetized, but this way I can read and drive signals in a few clock. Indeed using the Axi Stream is a bit slower, but use less LUT, am I right?

Depending on your suggestion I'll ask questions, thanks!