VexRiscv
VexRiscv copied to clipboard
SpinalHDL
RV32E support
After a discussion with @Dolu1990 , it was revealed that 50% of the gate count of a minimal VexRiscv is the register file, which is 32x32-bits. That's many registers.
The RV32E version of the specification cuts the number of registers down to 16, which should shrink the number of gates required by ~25%.
How much work is required to add support for RV32E?
Hi, So, RV32E is only about removing x16 to x31 and traping if an instruction try to access them. It can be done in less than 1 hour as it's realy minor changes.
Also, in the dev branch, for the riscv-contest i'm working on making VexRiscv more configurable in the number of stages to use less ressources. With the current changes you can go down to a 3 stage pipeline, but with some additional change, it can go down to 2 stages.
Got a two stages VexRiscv running zephyr and compliance tests :)
Very nice work!
FYI: Clifford Wolf checked in a riscv-formal change for a serial RISC-V CPU => super small size.
