VexRiscv
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Unused registers
I just want to report some unused flip-flop registers. They got removed during elaboration and since they are never used, they could also be removed? We should discuss how to handle these.
I found these for my current configuration:
- CsrPlugin_lastStageWasWfi
- DebugPlugin_firstCycle
- DebugPlugin_secondCycle
If I know how to handle these I could report more by trying out some other configurations.
In general, i'm not shy to have flip flop in the netlist which only have a purpose for simulation / debug purposes and which will be removed at synthesis. For instance : https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/VexRiscv.scala#L101
But the three regs that you point are dead code that i should remove, nice catch ^^