Avalon - QSYS SDRAM Controller problem

[nvitya]

avalon_qsys_sdram_16bit_errors.zip

Here a Quartus 18.1 project project including the signaltap_avalon_sdram_16bit_error.stp signaltap records. Theoretically if you open the project with File view, you can double-click on the signaltap file, and it will open the recordings. It contains 8 recordings, at the bottom you can select between the recordings.

What I see, that the QSYS SDRAM controller does not really controls the SDRAM sometimes, the only thing I see there that the ByteEnable[0..1] = 0 at the read (e.g. 0xC) when the SDRAM does not controlled.

Is it possible to force the ByteEnable to 0xF at the Reads? Or does it have another special meaning?