PipelineC
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JulianKemmerer
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Current [built in block/LUT RAM functionality ](https://github.com/JulianKemmerer/PipelineC/wiki/Automatically-Generated-Functionality#rams) does not support more than one read port. I.e. the supported dual port RAMs are one read port, one write port. ```c rd_val...
Opposite to https://github.com/JulianKemmerer/PipelineC/issues/79 where it is requested that command line arguments be able to set pragmas ...do the reverse as well. Allow pragmas in code to specify things from command...
Currently the tool outputs a final `top.vhd` with a `top` entity. Allow the user to specify any `top` name instead (cmd line, pragma, both?) Default should really be `pipelinec_top`...
Currently [FSM style](https://github.com/JulianKemmerer/PipelineC/wiki/FSM-Style) functions cannot be marked as top level `MAIN` functions. This is because of the `ready+valid handshake` that is built into the hardware implementation of these functions for...
Currently when selecting bits / slicing bit arrays the bounds must be constant., ex. ```c uint32_t x; // x(31 downto 0) uint1_t y = x(15); // y = x[15] uint16_t...
As show in https://github.com/JulianKemmerer/PipelineC/issues/87 it is possible to use variable names as functions (and arrays)... ```c uint32_t x; ... uint1_t b = x[3]; // Fourth bit of x(31 downto 0)...
FSM style functions typically create a new instance if not marked as SINGLE_INST. If not single instance, there should only ever be one `instance of a func per MAIN ~thread`...
Non block RAM based ROMs using muxing/LUTs can be done using [simple arrays](https://github.com/JulianKemmerer/PipelineC/wiki/Arrays). Using block rams for ROMs requires using a [RAM primitive](https://github.com/JulianKemmerer/PipelineC/wiki/Automatically-Generated-Functionality#rams) and simply never using the write enable...
Similar to how [async clock crossings](https://github.com/JulianKemmerer/PipelineC/wiki/Main-Function-Clock-Crossings) have a FIFO interface with valid/not empty/write+ready/not full signals... do same thing for a "~0 element fifo" same clock domain data transfer. Just becomes...
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A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.