Create FIFO-like comb. only single cycle handshake wire/clock crossing

[JulianKemmerer]

Similar to how async clock crossings have a FIFO interface with valid/not empty/write+ready/not full signals... do same thing for a "~0 element fifo" same clock domain data transfer. Just becomes a handshaking mechanism for moving data between func (as opposed to plain, unidirectional, non flow-control wires).

[JulianKemmerer]

Should be good for (FSM style arbitration, or not) sharing of N resources among M users.