PipelineC
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JulianKemmerer
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Relating to https://github.com/JulianKemmerer/PipelineC/issues/133 where muxes are synthesized for different data width
This is unnecessary since - though not ~perfectly accurate - PipelineC assumes all 2:1 muxes have the same path delay regardless of width of operands. Just restart the build after...
Ex. as opposed to ```c typedef struct my_func_outputs_t{ int x; int y; }my_func_outputs_t; my_func_outputs_t my_func(int a, int b) { my_func_outputs_t o; o.x = a; o.y = b; return o; }...
Just flatten one level - so typical `output_t` wrapper structs can naturally look like multiple ports in the VHDL Maybe can make a pragma to not always do? Related to...
For C this makes sense and folks know C keywords well... But here are the VHDL keywords to watch out for ``` abs configuration impure null rem type access constant...
Structs must use `tag_name == struct_alias` in struct definitions... ```c typedef struct tag_name { type member1; type member2; } struct_alias; ``` Otherwise you will get parsing errors as if type...
The integer modulo (remainder) Operator "%" insn't implemented... Demo code: ```cpp #include "intN_t.h" #pragma MAIN_MHZ test 100.0 int32_t test(int32_t a, int32_t b){ return a % b; // not implemented }...
```c triangle_t tri_ram[1]; triangle_t my_ram_main_tri_ram_RAM_SP_RF_0(uint0_t addr0, triangle_t wd, uint1_t we); ``` Fix to round 0 to 1 when doing log2 math
without then tool mistakenly reads from feedback signal like a register and is just wire connected to self connected to nothing... ```c uint8_t reg_wr_data; #pragma FEEDBACK reg_wr_data if(thing) reg_wr_data =...
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A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.