PipelineC
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JulianKemmerer
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
`Barbossa404` on Discord brought up how running tests/testbenches should be as easy as possible Consider for typical Verilog or VHDL you can have a setup like: ``` $ my_simulator my_verilog_testbench.v...
Right now we have areas of code that are intended to be performant, but we don't have benchmarks/profiling in place to know where our hot spots are/whether something is a...
Right now the various files use sys.exit(-1) in some places, which is less helpful than raising an exception. We should try to make more helpful exception messages, and move towards...
Consider this pipeline... ```c void frame_buffer_display() { vga_signals_t vga_signals = vga_timing(); pixel_t vga_pixel = user_func(vga_signals); pmod_register_outputs(vga_signals, color); } ``` Right now if the user's `user_func` is autopipelined then functionality is...
Currently each user/architecture is pretty easily able to put together a custom C "simulation" based on how their design works/is structured. They compile select parts of PipelineC designs typically with...
...but is there when lookup done by func name....wtf See SYN get pipeline map code...
Final testing ...
To have a sub directory of just HDL files - likely as `hdl/v/` and `hdl/vhdl/` And other separate directories for all the logs and other just produced by tools... Starts...
Ex. consider a derived FSM function `uint32_t add1(uint32_t)` invoked three times sequentially: ```c uint32_t add1(uint32_t x) { uint32_t rv = x + 1; __clk(); return rv; } uint32_t test1(uint32_t x)...
ex. wanting to have a FSM implementing the '+' operator. right now derived FSMs assume built in operators are always combinatorial logic / not themselves FSMs... Is complicated since havent...
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A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.