PipelineC
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A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Operator overloading can't use built in version of operator in definition of overload. Fix this to separate user's version of built in vs built in... Work around is to use...
* Requires a VHDL async "AXIS style FWFT" fifo implementation to use * Real hardware uses manufacturer macros * Previously took sync Verilog fifo and used that * Simulation should...
if have ex. ```c void some_func() { out = the_pipeline_func(in); } ``` where `in` and `out` are global wires - then, if `some_func` is selected for having IO registers added...
This also makes it easier to support multiple clocks For Verilator first probably...IIUC this needs newer Verilator than have worked with before Generate a generic testbench module with clock gen...
Ex. dont synth funcs that wont be pipelined (only occur in FSMs, or in stateful funcs, etc) relates to https://github.com/JulianKemmerer/PipelineC/issues/74
Code like below, but only for Vivado synthesis seen so far (2019.2, tried a few syn strategy options, didnt help)... ```c #pragma PART "xc7a100tcsg324-1" //#pragma PART "5CEBA4F23C8" //#pragma PART "LFE5U-85F-6BG381C"...
...so that the new `clock_crossing.h` header macros can be used. Current code gen looks like: ```c #define fast_to_slow_RATIO 4 #include "uint64_s_array_N_t.h" #define fast_to_slow_write_t uint64_s_array_1_t #define fast_to_slow_read_t uint64_s_array_4_t // Clock cross...
```c typedef enum enum_a_t { REQ, RESP }enum_a_t; typedef enum enum_b_t { REQ, RESP }enum_b_t; ``` Tool will fail to resolve VHDL instances of the literal 'REQ' and 'RESP' to...
WIP: Needs more testing. Use pycparser as submodule.
Add support for other preprocessors, ex. `clang -E` perhaps? Relates to https://github.com/JulianKemmerer/PipelineC/issues/56 A few places in code 'cpp' is hard coded...