PipelineC
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JulianKemmerer
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Want a pass that can combine sequential-looking FSM states that occur in the same cycle into one/as few combintatorial state transitions as possible (watching out for states that can't be...
It seems that in a foor loop, amount of stages for each iteration ca be fractional, it would be good to force at least one for iteration ``` for (i=0;...
Ex. global wire 'point': This makes it so you cant drive point.x from one main function, and point.y from another - both drive the entire wire, not just pieces.
Currently for basic things like adders ex. 32 bits is divided by the slices specified `[0.5] = slice into two pieces = two 16b stages` First this is annoying because...
Ex. ```c static uint32_t my_var; // Works if(cond){ // static uint32_t my_var; // Does not work my_var += 1; } ```
The [FIFO_FWFT implementation](https://github.com/JulianKemmerer/PipelineC/blob/master/fifo.h#L81) is correct in its use of valid+ready handshake signaling clock by clock. However because of the weird way that the implementation uses its 2 cycle latency BRAM,...
```c for (uint32_t i = 0; i < 32; i = i + 1) { ... } ``` needs to be ```c uint32_t i; for (i = 0; i <...
Related to allowing global variables to be top level inputs or outputs https://github.com/JulianKemmerer/PipelineC/issues/123 Allow special clock enable and reset signals marked this way too maybe? Otherwise, work around like in...
TL/DR signals for user generated clocks with top level names, ex. clk_60p0hz, don't show up in constraint `get_nets` for all tools. Ex. Graphics work uses [CLK_MHZ pragma](https://github.com/JulianKemmerer/PipelineC/wiki/Pragmas#globally-visible-wires) to mark a...
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A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.