PipelineC
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Allow bit slicing to behave like random array access/muxing
Currently when selecting bits / slicing bit arrays the bounds must be constant., ex.
uint32_t x; // x(31 downto 0)
uint1_t y = x(15); // y = x[15]
uint16_t z = x(15, 0); // z = x[15:0]
That is 15
and 0
must be compile time constants.
Otherwise this is a type of random access...
// Unimplemented equivalent array syntax
uint1_t rand_rd = x[rand_index]; // Unimplemented rand access read
x[rand_index] = something; // Unimplemented rand access write
// Even constant indices are still yet to be implemented
uint1_t y = x[15]; // Unimplemented constant array read
x[15] = something; // Unimplemented constant array write
Random single bit access looks identical to what can be hand written instead using a array of bits.
// Explict arrays of bits work as expected
uint1_t x[32]; // ~like x(31 downto 0)
uint1_t rand_rd = x[rand_index]; // 32->1 mux with rand_index as select
x[rand_index] = something; // Rand access write, more muxing
Arrays that are accessed with non constant indices (i.e. random access) infer muxes. Also see bit manipulation functions for converting bit arrays to unsigned values (ex. uint32_t uint1_array32_le(uint1_t x[32])
)
Random access for multi bit slices is more complicated. See ex. Verilog index part select where only part of the range can be non constant. (ex. width of 8
is still constant below).
dword[0 +: 8]; // Same as dword[7:0]
assign byte = dword[(i*8)+7 : i*8]; // Not valid Verilog
// Use the indexed part select
assign byte = dword[i*8 +: 8];
All of this will look alot like/use existing array support in implementation - just more edge cases for treating integers and such implicitly as arrays of bits + complications with multi bit slices...