PipelineC
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JulianKemmerer
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Cannot use `case` statements yet - must write as if-else branches. Would open up opportunities for better N-1 mux infer... but how to autopipeline - similar to DSPs?
Currently the tool makes a new output directory for each run. That is unless the user specifies a fixed `--out_dir`. However, it then becomes the users responsibility to 'clean'/remove cache...
Currently clock crossings are declared like so https://github.com/JulianKemmerer/PipelineC/wiki/Main-Function-Clock-Crossings _Now that https://github.com/JulianKemmerer/PipelineC/issues/73 was completed, its less of an issue for weirdest old `clock_crossing/the_wire.h` style ..._ ```c // Volatile buffered volatile type_t...
Primarily for making large chunks of untimed ~'constant' logic anywhere in the design work with no extra manual registers from the user added.
Note that `accumulate` isnt a perfect example below since [actually has exotic pipelining possibilities](https://github.com/JulianKemmerer/PipelineC/issues/81) for integer math. _____ Consider a multiply (can be pipelined) and accumulate (cannot be pipelined, [normally](https://github.com/JulianKemmerer/PipelineC/issues/81))...
Obvious one should be for ex. `./src/pipelinec my_file.c --pragma MAIN_MHZ my_main 100.0` Instead of always needing `#pragma MAIN_MHZ my_main 100.0` in code. Error if pragmas dont match etc would be...
Want to detect and fix things like for ex. below where the same functionality can be done with '1 multiplier and more muxing' instead of '2 multipliers and fewer muxing'....
Ex. want to support like `-DMYMACRO` to preprocessor
Files exist on disk for all the various pipeline configurations that are tried. But only one is being simulated at a time. Fix GET_SIM_FILES to be similar to GET_VHDL_FILES_TCL_TEXT_AND_TOP so...
### Discussed in https://github.com/JulianKemmerer/PipelineC/discussions/42 Originally posted by **bartokon** November 9, 2021 Hi, I'm thinking if it is possible to create a fake part with fake timings, so whole place and...
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A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.