Implement autopipelined BROMs

[JulianKemmerer]

Non block RAM based ROMs using muxing/LUTs can be done using simple arrays.

Using block rams for ROMs requires using a RAM primitive and simply never using the write enable on the RAM, making it a read only. However, this restricts ROM usage timing/pipelining/latency to being specified by the user - needing to specify if the RAM has input/output regsiters etc - is not autopipelineable.

Instead introduce 'autopipelineable pure function ROM primitive functions' that do not specify input and/or output regs. Instead similar to other pure funcs - pipeline regs are added as needed by the tool.

[JulianKemmerer]

Apparently putting output registers on the RAM can make Vivado adding pipelining in the RAM, helping for large RAMs...maybe URAM only? ...neat...