chisel2-deprecated
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Although large priority encoders have been fixed in C++, a new test should be added to prevent regression as we move to chisel 3.0.
Consider the following case: ``` scala class Toy extends Module { val io = new Bundle { val in = UInt(width=8).asInput val out = UInt(width=8).asOutput } val myDPT = Module(new...
Let's say I have a piece of Verilog IP described thusly: ``` verilog module my_ip( input my_input, output my_output ); // Analog or otherwise non-Chisel-y functionality; port names can't be...
``` scala UInt(1) // current syntax for constructing a UInt literal 1 // vs. UInt(width=1) // current syntax for constructing a wire of width 1 UInt(null, 1) // unadvised but...
``` scala class Toy extends {val myEarlyReg = Reg(UInt())} with Module { val io = new Bundle { val in1 = UInt(width=2).asInput val out1 = UInt(width=32).asOutput } io.out2 := myEarlyReg...
Latest FPGAs support true dual-port memories. True dual port means two independent ports to the memory where you can switch the direction. I'm not sure how this could be added...
I can't get a Vec working as a ROM. I'm sure I could work around it, but this doesn't seem like correct behavior. Is there a bug, is the documentation...
There is lots of useful stuff in ChiselUtil, but it's really easy to not know that this exists, much less how to use it. This useful library of modules should...
I'm not sure if this is supported or legal Chisel, but it is possible to write a Vec of a Vec and it will compile and run properly in C++...
The description for the seqRead in the Mem section (9) is out of date. The current text describes using the output register for seqRead. Chisel currently leaves the output alone...
