<> is not context aware

[sdtwigg]

Consider the following case:

class Toy extends Module {
  val io = new Bundle {
    val in  = UInt(width=8).asInput
    val out = UInt(width=8).asOutput
  }

  val myDPT = Module(new DoublePassThrough)
  myDPT.io.ptin1 <> io.in
  myDPT.io.ptin2 <> myDPT.io.ptout1 // PROBLEMATIC LINE
  io.out <> myDPT.io.ptout2
}

class DoublePassThrough extends Module {
  val io = new Bundle {
    val ptin1  = UInt(width=8).asInput
    val ptout1 = UInt(width=8).asOutput
    val ptin2  = UInt(width=8).asInput
    val ptout2 = UInt(width=8).asOutput
  }
  io.ptout1 <> io.ptin1
  io.ptout2 <> io.ptin2
}

The expected behavior in that data flows as such: io.in -> io.ptin1 -> io.ptout1 -> io.ptin2 -> io.ptout2 -> io.out

However, the <> assignment does not consider what module it is in when making the assignment, merely what the owners of the associated nodes are. Thus, the problematic line is interpreted as actually occurring inside of the DoublePassThroughModule and thus as equivalent to the statement: io.ptout1 := io.ptin2, which is incorrect.

This is similar to erroneous assumptions that were made in past editions of addBindings.

[sdtwigg]

This function handles all the edge cases properly I think https://github.com/sdtwigg/gama/blob/b268966af13312e7383e4821b6af4fc1a23fe5b4/chiselfrontend/src/main/scala/internal/BiConnect.scala#L39 None in the matching means an internal connectable node (like wire or reg), Some(Input/Output) is a port.