True dual-port on-chip memories support

[schoeberl]

Latest FPGAs support true dual-port memories. True dual port means two independent ports to the memory where you can switch the direction. I'm not sure how this could be added to the current memory class. Probably we need something new here with some rethinking how current memory technologies can be represented in general, e.g., can we define read during write is unspecified? Can this even be expressed in Verilog? Probably not. Or that there are no asynchronous memories anymore available in FPGAs.

This is not a request for a quick fix, but intended to start the discussion. If this is the wrong place to discuss this, just close the request I can mail this to the mailing list.

[ucbjrl]

Wait for Chisel 3.0