chisel2-deprecated
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So I've spent the last n days debugging someone else's Chisel/Verilog, which generally exhibited this symptom: Verilog testbench passes in Vivado (behavioral + post synthesis) Behavioral Verilog testbench passes in...
It would be useful to have an option _not_ to prepend the module name to the names of class members in the C++ emulator. I'm trying to test several modules...
I'm experiencing a `java.lang.UnsupportedOperationException: empty.head` that is caused by a Reg(Vec()) of size 0. ``` scala val num_stages = 0 val r_valids = Reg(init = Vec.fill(num_stages) { Bool(false) }) ```...
It would be really nice to be able to put in a flag that would allow you to check to see if any module ports you don't expect to be...
I'm also being stopped by exit code 139 problems -- translates to an illegal memory access by the C++ simulation. My Chisel trace is as follows: Chisel.TestApplicationException: test application exit...
I defined a value "config" in one of my Chisel modules exactly as below. When I generated Verilog output from this module it created a wire in Verilog called "config."...
I am getting an undeclared variable error for the following: ``` scala class UserMod extends Module { val io = new Bundle { val out = UInt( OUTPUT,8 ) }...
The catting a UInt of width 0 onto a value causes strange results in c simulation ``` scala class UserMod extends Module { val io = new Bundle { val...
Any time you use scala extractor syntax (sometimes called doing an unapply), identifiers that start with an uppercase letter are assumed to be stable (already bound to a value) identifiers....
We are working on our CS250 project with many wires connections and a parameter to control the number of row modules. When we increase number of rows to a specific...
