chisel2-deprecated
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Is it possible to add support for building asynchronous circuits and also provide some tutorial on how this can be done on Chisel.
In section 2 of the manual, Nodes, it indicates that Data, Reg and Mem extend updateable. Is this just out of date or reflective of the desired class structure? I...
Is it possible to release a easy to use MS Windows toolchain for Chisel.
Feature request to have a flag passed in to emulator that will detect whether overflow has occurred in an arithmetic operation and print a warning message to stderr in the...
Given the following code: ``` scala val clkA = new Clock() val clkB = new Clock() val regA = Reg(outType=Bool(), init=Bool(false), clock = clkA) val regB = Reg(outType=Bool(), init=Bool(false), clock...
I have a problem with compiling a module that use two domain clock. I'm re-writting the AsyncFifo to include the ability to flush it. Here the code :: ``` Scala...
Hey all, I'm in the process of porting over some Matlab FFT code into Chisel for hardware generation. In Matlab, I've calculated a bunch of constant values that I would...
It would be greatly beneficial if Chisel had a high impedance state for wires. This would be equivalent to the Verliog `1'bZ`.
Instance names generated by Vecs tend to look like this: ``` scala instance instance_1 instance_2 ... ``` From a scripting standpoint, it would be great if they could instead look...
richard@richard-HP-ENVY-15-Notebook-PC:~/Rocket/rocket-chip$ cd emulator richard@richard-HP-ENVY-15-Notebook-PC:~/Rocket/rocket-chip/emulator$ make debug cd /home/richard/Rocket/rocket-chip && java -Xmx2048M -Xss8M -XX:MaxPermSize=128M -jar sbt-launch.jar "project rocketchip" "elaborate Top --noIoDebug --backend c --configInstance rocketchip.DefaultCPPConfig --targetDir emulator/generated-src-debug --debug --vcd --ioDebug" sbt...
