Do blackboxes really need to name all IO pins with "io_"?

[ben-k]

Let's say I have a piece of Verilog IP described thusly:

module my_ip(
  input my_input,
  output my_output
);
  // Analog or otherwise non-Chisel-y functionality; port names can't be modified!
endmodule

I'd love to instantiate this in Chisel using BlackBox, but the best I can do is:

class my_ip extends BlackBox {
  val io = new Bundle {
    val my_input = Bool(INPUT)
    val my_output = Bool(OUTPUT)
  }
}
val ip = new my_ip

The generated Verilog unfortunately then looks like this:

my_ip ip(
  input io_my_input,
  output io_my_output
);

Which doesn't match the module definition. Is there an (undocumented) way to make the Verilog generated from BlackBox IOs not start with the string "io_"? Otherwise you can't really plug in arbitrary black-boxed modules in the way that I think is intended.

[CuppoJava]

We're working on that feature for Chisel 3.0. Perhaps someone else knows of a magic workaround for getting it to work in Chisel 2. -Patrick

On Wed, Apr 15, 2015 at 9:20 PM, ben-k [email protected] wrote:

Let's say I have a piece of Verilog IP described thusly:

module my_ip( input my_input, output my_output ); // Analog or otherwise non-Chisel-y functionality; port names can't be modified!endmodule

I'd love to instantiate this in Chisel using BlackBox, but the best I can do is:

class my_ip extends BlackBox { val io = new Bundle { val my_input = Bool(INPUT) val my_output = Bool(OUTPUT) } }val ip = new my_ip

The generated Verilog unfortunately then looks like this:

my_ip ip( input io_my_input, output io_my_output );

Which doesn't match the module definition. Is there an (undocumented) way to make the Verilog generated from BlackBox IOs not start with the string "io_"? Otherwise you can't really plug in arbitrary black-boxed modules in the way that I think is intended.

— Reply to this email directly or view it on GitHub https://github.com/ucb-bar/chisel/issues/397.

[albert-magyar]

In Chisel 2, you can set the name (as emitted by a backed) of any wire to be whatever you like by invoking setName(name: String).

[ben-k]

Thanks, I'll demote this to a documentation request.