Vec of Vec? Verilog generation is broken.

[ccelio]

I'm not sure if this is supported or legal Chisel, but it is possible to write a Vec of a Vec and it will compile and run properly in C++ emulation, but it will fail to compile in Verilog.

The signal names of the inner Vec get duplicated (and not properly name-mangled), so the compiler pukes on the duplicate I/Os ("already defined as a port"). It looks like, for some reason, the outer Vec iterates are not incrementing its index/name.

Is this something we should catch and error out from in C++ land? Or should the Verilog bug be addressed?

class PortIn(length:Int) extends BOOMCoreBundle {
   val prs = Vec.fill(length) {UInt(width=7)}
}

class BusyTableIo(width: Int, length: Int) extends Bundle {
   val read = Vec.fill(width) { new PortIn(length).asInput }
   ...
}

Verilog:

module BusyTable(input clk, input reset,
    input [6:0] io_read_0_prs_0,
    input [6:0] io_read_0_prs_1,
    input [6:0] io_read_0_prs_2,
    input [6:0] io_read_0_prs_2,
    input [6:0] io_read_0_prs_1,
    input [6:0] io_read_0_prs_0,
    ...

Also, if Vecs of Vecs are verboten, I would love to get feedback on how to properly write this code in a more proper manner.