chisel2-deprecated
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ucb-bar
I wanted to create a register of an aggregate type specifying default values but found no way to do it inline. How can I do this? ``` val r =...
It would be beneficial for the purposes of writing frontend libraries that wish to reflect on Chisel modules and nodes over multiple passes or functions to be able to store...
Testing frameworks like JUnit are more self-contained and simpler to use: you just declare a test, define set-up and tear-down functions, and the system automatically finds all the tests to...
https://chisel.eecs.berkeley.edu/2.2.0/getting-started.html Images and some symbols are not appearing for me. Tested this on multiple browsers in OS X.
Just wondering if there can be a chisel-dev google group to discuss what to work on/priorities/bugs Think its better to keep separate from chisel-users
The problem to solve here is that if I've developed a module that depends on an input parameter and I want to test it against multiple inputs. an example could...
I find quite hard to navigate the sources of Chisel at the moment. What do you think about moving semantically different files under specific packages? You could think that `UInt`...
Running the following chisel code produces a Verilog syntax error. At a high level, this code just takes the output of some submodule (BiplexFFT) and computes the power. ``` Scala...
It will be possible to fast link to you, i.e. via a gitter.im channel on this repo. This will be to follow the status of the project and for "community...
Look at "FIXME Chisel" in https://github.com/ucb-bar/hwacha/blob/5cad463d5e4aee2271c7e31d68d683c397300caf/src/main/scala/vmu.scala. I had to use the actual ready signal coming out of a children's module rather than doing vvaq.io.deq.fire() or vpaq.io.enq.fire().
