chisel2-deprecated
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Running into warnings: ``` [info] Compiling 66 Scala sources to /home/drom/work/github/usb-bar/chisel/target/scala-2.11/classes... [info] 'compiler-interface' not yet compiled for Scala 2.11.7. Compiling... [info] Compilation completed in 14.46 s [warn] /home/drom/work/github/usb-bar/chisel/src/main/scala/Parameters.scala:455: abstract type...
This code behaves differently in Chisel2 and 3. It would be good if the compatibility checker would catch it. ``` io.rocc.resp.ready := !(wb_reg_valid && wb_ctrl.wxd) ... csr.io.rocc io.rocc ``` In...
**Feature request:** It would be nice to mux Bundles in when statements, e.g., ``` when (somesignal) { bundle otherBundle } .otherwise { bundle defaultBundle } ``` The idea would be...
``` scala class UserMod( bw : Int ) extends Module { val io = new Bundle { val in = UInt( INPUT, bw ) val out = UInt( OUTPUT )...
I get this stack trace when running a medium sized design. ... Exception during evaluation: error: ConcreteSInt(4140379555, 32) bad width 32 needs 33 @[Decoupled.scala 127:17] Expression Evaluation stack 0 fifo_diag_1_1.Queue_1_1.ram_sim_value.T_71.data:MemIO...
Hello, I am using the OrderedDecoupledHWIOTester for testing, I check the wavform, it seems the output.ready signal maintain high, Is it possible to insert random bubble for the signal, so...
test output, with latest chisel version: STEP 1 -> 13 output test event 5 testing out.bits.low = 33, should be 33 output test event 5 testing out.bits.high = 24, should...
I am writing an interrupt controller in Chisel. The following function determines the highest priority pending interrupt. Each interrupt source is represented by a IRQStatusReg and the combined register file...
Chisel seems to not like using `else` and `else if` in Verilog code, and this has caused a problem with my RAM block not being inferred by the Vivado synthesizer...
