chisel2-deprecated

chisel2-deprecated copied to clipboard

Added blocks for input, output, and input-output timing closure

8

Created two Chisel blocks for timing closure. These blocks are designed for use in decoupled IO designs, to make closing timing on module boundaries easier.

hutch31

Fixed AsyncFifo so reset not tied to 0

4

Previous logic was ``` if reset = 1 s1_rst = 0 else s1_rst = reset // reset = 0 ``` changed to ``` s1_rst = reset ```

da-steve101

I accidentally mixed UInt and Vec assigns ``` scala class UIntToVecAssign extends Module { val io = new Bundle { val in = UInt( INPUT, 64 ) val out =...

da-steve101

Invalid Reg width generation leads to bad bounds in generated Verilog

8

**TL,DR: There needs to be a width check on signals before generating the final code.** --- I've found the following circuit generates erroneous Verilog code (I didn't check C++). It...

ccelio

Register size inference

12

The following code should size a register for 4 bits by using an UInt constant: val reg = Reg(UInt(15)) reg := reg + UInt(1) io.result := reg However, the resulting...

schoeberl

Cocotb directives in Verilog backend

2

I'm using [cocotb](https://github.com/potentialventures/cocotb) to write my testbench. Because it's in python and it's easier than writing verilog testbench. But to simulate verilog generated by chisel I have to modify the...

Martoni

Changed Vec cloneType

11

Each element's type is properly cloned. See #392

shunshou

setModuleName is scary... (results in wrong Verilog)

1

Chisel doesn't do a second pass on checking for module name uniqueness if setModuleName is used. I have a parameterizable LUT module that takes in a list of values I...

shunshou

Move emitRef from Verilog to backend

5

Currently not passing the tests as for some test cases are named twice and hence index does not start at 0. Not sure where this is happening, but seems like...

da-steve101

Vec clone method incorrect

1

``` scala class Toy extends Module { val io = new Bundle { val in1 = UInt(width= 2).asInput val in2 = UInt(width=16).asInput val select = UInt(width= 2).asInput val out1 =...

sdtwigg