chisel2-deprecated
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So... as far as I understand it, not many people have actually played around with multiple clock domains and it only works when clocks are integer multiples of each other......
What is the difference between --backend fpga and --backend v? I was expecting that --backend v would black box the Chisel mems (generated verilog would just have modules + port...
chisel-torture generated the following Chisel file today ``` import Chisel._; object Torture { def main(args: Array[String]): Unit = { chiselMain(args, () => Module(new Torture())); } } class Torture extends Module...
Edit: Nevermind. I guess I was doing something silly. But I'd still like to know what isDebugMem, isInlineMem, and isVCDMem do... Edit2: When isDebugMem is true, write to mem still...
This sample code is greatly chopped down from the actual reconfigurable logic design the bug was found in. This bug is a showstopper for reconfigurable logic designs of anything but...
For Patmos, we use a customized emulator, such that we can a) initialize memories as needed and b) to emulate peripherals (e.g., external memory or the UART). The Chisel code...
We have been working recently on Chisel SystemC backend to support all signals and ports like Decoupled and Valid, also we improved the automatic generation of the SystemC wrappers. Now,...
When you use 'peek' and the like in the Tester class, the outputs are in hexadecimal. It would be great if you could optionally have Chisel emit them in decimal,...
I have a scala class ModInt that looks like: class ModInt extends Bundle { val dat = new BigUInt() val mod = new BigUInt() def +... } and BigUInt looks...
When creating a node literal such as: ``` scala val tmp = UInt(0, 4) val tmpReg = RegInit(UInt(0, 4)) tmp := tmpReg ``` Gives "Real node required here, but 'type'...
