chisel2-deprecated
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Just found a bug in something I was writing which took a while to spot. Essentially came down to: ``` scala class UserMod extends Module { val io = new...
I am trying to create a literal from a generated type. Here is what I have so far: ``` scala import Chisel._ class GenTypeIssue [T new UserTest(c) ) } }...
fixes #571 Adds a method getLit(BigInt) to get a literal with that value I think getting a lit directly rather than passing around the object is the way to go
I'm trying to make a very generic counter template, where given a set of user parameters, I'll get back a counter with just the right amount of IO for control...
As soon as the chisel code includes registers the Verilog backend generates unused wires or a chain of unused wires respectively (see the commented assignments of the generated code below)....
risingedge function is given as example in Chisel tutorial : ``` scala def risingedge(x: Bool) = x && !Reg(next = x) ``` It's a really usefull function I redefine in...
Chisel should issue a warning for modules with no connected ports. Prompted by issue #545.
Being able to define bits as unknown (like Verilog Xs) could make some pieces of RTL easier to test. For example, a memory's read port data value can return an...
It would be nice to have a type (like UInt, Bool) for enum wires which also does static type checking (for example, to make sure I don't accidentally assign Animal.Duck...
Unions are a very useful feature for hardware design. Other languages support tagged unions which are even more powerful than C unions for hardware design. Chisel should provide one.
