cva6
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openhwgroup
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Illegal counter access while the hart is running in...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Debug mode entry reason field, `cause`, of `dcsr` should...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Instruction retire counters `minstret` and `minstreth` are incremented and...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Vector mode field, `MODE`, of `mtvec` holds reserved values....
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Fence of I/O implies memory field `FIOM` of `menvcfg`...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Vector base address field, `BASE`, of `mtvec` or `stvec`...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Virtualization mode only field, `v`, of `dcsr` is set...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Exception program counters, `mepc` and `sepc`, and debug program...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description EBREAK instructions generating breakpoint exceptions update debug CSRs `dpc`...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Trap-return instructions, `MRET` and `SRET`, set `MPRV` of `mstatus`...
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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux