cva6

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[BUG] Unexpected Behavior in CVA6 with Illegal Instruction Altering Register Values

2

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description **Describe the bug:** In the CVA6 RISC-V core implementation,...

youzi27

[BUG] Incorrect 'minstret' update upon encountering an illegal instruction

4

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description **Describe the bug:** In the CVA6 architecture, executing an...

youzi27

Log Failure Despite Passing Tests: AXI4_RESET Violation in CVA6 Repository

2

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description ### Description I have executed a series of commands...

akalboussi

[BUG] Passive mode of AXI agents does not work anymore

3

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description When using cva6.py with `--axi_active="no"` and vcs-uvm tesbench simulation...

Gchauvon

Condition coverage limitation

6

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description In the frontend.sv, the line 373 does not appear...

JeanRochCoulon

RVFI : Missing CSRs in the RVFI implementation

5

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Hello, Thanks to @yanicasa, now the RVFI implement CSRs...

AyoubJalali

Hello, this MR related to display functional coverage results for ISA, CSRs and TRAPs, another related MR while be open to report the results in dashbord

AyoubJalali

Bumps [verif/core-v-verif](https://github.com/openhwgroup/core-v-verif) from `3728f31` to `4e6e860`. Commits 4e6e860 Merge pull request #2442 from ThalesSiliconSecurity/fix/spike-version-reporting 2decd1c Merge pull request #2436 from MikeOpenHWGroup/MikeOpenHWGroup-fix-um-links 1888e11 Update intro and user manual links. 22d4cd3 Update...

dependabot[bot]

Parametrize AXI assertion module to disable invalid assertions with HPDCache. Implementation of the HPDCache parameter in env_cfg to configure the AXI coverage model.

AEzzejjari

fix tval in mmu

4

Use vaddr for tval instead of paddr when translation is enabled

AngelaGonzalezMarino