openhwgroup
Additional alignment constraints of the vector base address are not honored in vectored mode
Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
Bug Description
Vector base address field, BASE, of mtvec or stvec doesn't honor the additional alignment constraints imposed by the implementation when in Vectored mode. The example where this applies to mtvec is not shown here.
RISC-V Specification
Unprivileged ISA: 20191213 | Privileged Architecture: 20211203 | External Debug Support: 0.13.02
The mtvec register is an MXLEN-bit WARL read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE).
The mtvec register must always be implemented, but can contain a read-only value. If mtvec is writable, the set of values the register may hold can vary by implementation. The value in the BASE field must always be aligned on a 4-byte boundary, and the MODE setting may impose additional alignment constraints on the value in the BASE field.
An implementation may have different alignment constraints for different modes. In particular, MODE=Vectored may have stricter alignment constraints than MODE=Direct.
The stvec register is an SXLEN-bit read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE).
The BASE field in stvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: the address must be 4-byte aligned, and MODE settings other than Direct might impose additional alignment constraints on the value in the BASE field.
Example Scenario
As shown below, the following sequence of instructions happens:
CSRRS x9, stvec, x9 -> CSRRSI x1, stvec, 1
The instruction CSRRSI x1, stvec, 1 is decoded at t_id and executed in machine mode resulting in updating the architecture state at t_arch_update. As a result, a wrong value of the BASE field of stvec is read considering the additional implementation alignment constraint of 64 * 4 bytes.
Steps to Reproduce
Git Hash: de2e254c | TARGET_CFG: cv32a6_imac_sv0 | VCD: issue_11.zip
Component
Component:RTL
Product: Questa OneSpin Solutions App: Questa Processor App Tool's version: 2024.1_1
