Question - Verilog-Ethernet vs 1G/2.5G Ethernet Subsystem

[Beauxrel]

I was wondering if this project could be used as a replacement for the Ethernet subsystem provided by Xilinx in Vivado. The Subsystem holds a MAC, Ethernet Buffer and PCS/PMA module. The MAC is not free (~$600), so I am looking for alternate ways to get the same functionality.

Thanks!

[alexforencich]

Best option at the moment is to use the MAC from this repo in combination with the (free-of-charge) Xilinx 1G PCS/PMA core. See the VCU108 or VCU118 example designs for how to wire this up. Eventually I'll probably have a 1G PCS/PMA in this repo as well, but I don't have a timeline for that at the moment.

[Beauxrel]

Codecov Report

All modified and coverable lines are covered by tests :white_check_mark:

Project coverage is 88.63%. Comparing base (dd3b2fa) to head (42924dc).

Additional details and impacted files

@@            Coverage Diff            @@
##             master     #296   +/-   ##
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  Coverage     88.63%   88.63%           
  Complexity      575      575           
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  Files             8        8           
  Lines          1302     1302           
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  Hits           1154     1154           
  Misses          148      148           

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