Wrong bit with on 10G MAC Tx start_packet_reg

[drewranck]

https://github.com/alexforencich/verilog-ethernet/blob/master/rtl/axis_xgmii_tx_64.v#L174\

Should be reg [1:0]. I noticed this on a private unit simulation I did in Vivado XSIM with a Xilinx GTY. The truncation on [1] on this signal means the 4B misaligned 10G encoding don't report packet starts.

I can fix this if you're willing to take a PR.