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VUnit
VUnit is a unit testing framework for VHDL/SystemVerilog
The CHECK_EQUAL_VARIANCE macro in the vunit_defines.svh file does the following assertion. ` define CHECK_EQUAL_VARIANCE(got,expected,variance,msg=__none__) assert (((got) < ((expected) + (variance))) && ((got) > ((expected) - (variance)))) else .... ` I...
 There is a problem with the verification component. When I try to push_axi_stream and pop_axi_stream the m_axis_tready_s goes low for no reason. I want to know is this is...
Anyone else notice really slow scrolling behavior on the documentation static website? I don't experience this on any other Read the Docs host, just VUnit.
In upcoming releases (#763), we expect to implement #559 (see #757 and #764), which will introduce some changes to the management of builtins. Builtins are the HDL libraries distributed with...
Attempting to compile using VHDL-2019 results in the following error: Invalid VHDL standard 2019.  This can be fixed by updating activehdl.py as follows:  @staticmethod def _std_str(vhdl_standard): """ Convert...
Added support for Cadence Xcelium simulator which is the successor of incisive. - Extended incisive.py to support xcelium simulator and maintain backwards compatibility with incisive - Support vunit options disable_ieee_warnings...
Hello Lars and Vunit maintainers, this pull request adds support for the Metrics simulator (DSim) to Vunit. So far only Verilog and SystemVerilog designs can be simulated with Metrics, however...
Some further modifications to #520. This PR is just style, it should have no impact in behaviour or CI.
From https://github.com/VUnit/vunit/pull/507#discussion_r328261564: > [@kraigher] > This is really an old mistake that I think we made that I might want to change. It would have been better not to add...
This PR provides compliance testing of VUnit VCs and VCIs according to the following rules: Rule: The file containing the VCI package shall only contain one package Rationale: The VCI...
