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VUnit
VUnit is a unit testing framework for VHDL/SystemVerilog
I will use this issue to keep track of the status of my efforts to add cocotb support to VUnit and receive suggestions and feedback. I am new to VUnit...
@LarsAsplund, @kraiger and @umarcor, I would like to propose a broad strategy for co-simulation with VUnit. I really like what @umarcor has been working on, but I think his approach...
@LarsAsplund and @umarcor, here is the discussion I promised on Gitter. In their current form, I find the storage data structures for `string_ptr` and `integer_vector_ptr` a bit confusing. I think...
I mentioned this on Gitter, but I think it might be best to create an issue to consolidate the discussion and make sure comments don't get lost. I would like...
We are importing the DPI-C "getenv" function in our verilog code to be able to grab some environment variables at runtime, and an unnecessary warning is generated by `tests/unit/test_verilog_parser.py` https://github.com/VUnit/vunit/blob/master/tests/unit/test_verilog_parser.py#L180...
I am new to VUnit and am trying to run through the simple example given in the documentation page. I am running on a Windows 10 platform with cygwin64 installed...
I am having problems using the AXI VCs in activeHDL 11.1 where I see the the simulator times out from the VUnit watchdog. In ModelSim and GHDL, I do not...
Hi! I faced this problem while trying to add an additional string in `"modelsim.vsim_flags"` sim option in different test cases. Basically, I have a default configuration for my entire testbench...
I'm currently writing test benches for code that handles 32 bit addresses. In my test bench I'm writing the addresses a hex string eg. X"deadbeef". However, when a check_equal fails...
I have two source files that represent two versions of a block: vita_49_2_sink_buffer_output_logic_read_2_0.vhd vita_49_2_sink_buffer_output_logic_read_1_0.vhd As the name suggests they represent two versions of the same block in my vunit project....
