cva6

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[BUG] PMP config can not select `NA4` mode while granularity is set to 4

3

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description While the granularity of the PMP can determine by...

riscv914

Bump core/cache_subsystem/hpdcache from `25ffa34` to `b4519e7`

4

Bumps [core/cache_subsystem/hpdcache](https://github.com/openhwgroup/cv-hpdcache) from `25ffa34` to `b4519e7`. Commits b4519e7 Add new technical paper in README f5b00c6 Update the documentation section of the README afd6342 Update the changelog file 433011f New HPDcache...

dependabot[bot]

[BUG] PMP benchmark/test is broken

2

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description A couple of years ago, CVA6 did manage to...

Moschn

[Scratchpads] Needed packages for scratchpads and ahb peripheral bus

14

This PR aims at integrate features developed by Bosch : - Data scratchpad: #1808 - Instruction scratchpad: #1809 - AHB peripheral bus: #1810

CoralieAllioux

core/store_buffer.sv: make address check XLEN dependant

7

Address check is currently performed on [11:3] which (a) is (very slightly) suboptimal on rv32, but more important (b) hides the intent of the check. Suggested-by: Pierre Ravenel

fpetrot

Make OPERANDS_PER_INSTR part of build_config

1

This parameter was used in one file; it is used in several files since https://github.com/openhwgroup/cva6/pull/2395 We  should: - Add an `unsigned int OperandsPerInstr` field to [cva6_cfg_t](https://github.com/openhwgroup/cva6/blob/master/core/include/config_pkg.sv#L351) (but **not** [cva6_user_cfg_t](https://github.com/openhwgroup/cva6/blob/master/core/include/config_pkg.sv#L201)) -...

cathales

Add AW lock register to handle W FIFO push signal

2

The original implementation uses the AW handshake as the logical condition for a push into the W channel FIFO. However, this choice implicitly assume that the AW handshake will take...

ricted98

[TASK] Upgrade Spike tandem with DPI functions to access CSRs and to update with Interrupt/Debug signals

4

### Is there an existing CVA6 task for this? - [X] I have searched the existing task issues ### Task Description To align RTL and Spike-Tandem in some test scenarios...

AnouarZajni

[Pmp] Verif plan TXT

4

This PR aims at resolving task https://github.com/openhwgroup/cva6/issues/1447 Here's a first version of the Verification Plan of PMP, in txt format. It is split in 2 files: - verif/docs/VerifPlans/PMP/pmp_verif_plan.txt - verif/docs/VerifPlans/PMP/pmp_verif_plan_features.txt...

CoralieAllioux

[BUG] CVA6 core throw `Store Address Misaligned` while address for `Load-Reserved` is misaligned

1

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description When executing Load-Reserved instructions (e.g. `LR.D`) with a misaligned...

riscv914