Automatic sorting and grouping for generated outputs

[mkorbel1]

Motivation

Currently, the order of module and signal declaration within generated outputs can appear somewhat random, being largely dependent on the order of construction and parsing. There may be a better way to sort and organize module and signal declarations based on the connectivity between them. For example, having things that depend on inputs near the top and that generate outputs near the bottom, and grouping logic together which are interdependent, could result in prettier and more readable outputs.

Desired solution

Add an ability for Synthesizers to organize module and signal declarations more intelligently based on their connectivity to each other and the ports of the module.

Alternatives considered

No response

Additional details

No response

[mkorbel1]

Perhaps grouping into clusters first (maybe somthing like https://en.wikipedia.org/wiki/HCS_clustering_algorithm), then topological sort between the clusters and within each cluster could get us close?