amaranth

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Out-of-box CXXSim fails on MacOS

1

The user needs to install and put Homebrew's clang on the path for CXXSim to work out of the box on MacOS, otherwise, the following simple example fails. ```python """...

BracketMaster

Stream Abstraction for nmigen.lib

18

There is a desire to have a generic stream abstraction in `nmigen.lib` which can be used / presented by the `nmigen-stdio` cores (among others). This issue exists to capture discussion...

awygle

pysim: option to capture simulation output in a python object

9

Would it make sense to have a way to capture simulation output in a python object, rather than having to use a vcd file and a separate reader program? I'm...

mszep

class Memory: add reset_less parameter that will not initialize memories with 0 value in generated RTL.

30

**Issue by [Fatsie](https://github.com/Fatsie)** _Saturday Nov 16, 2019 at 13:21 GMT_ _Originally opened as https://github.com/m-labs/nmigen/pull/270_ ---- I am using nmigen for generating RTL to be implemented on an ASIC. In an...

nmigen-issue-migration

Feature request: Integrate logic analyzer into the language Signal(trace=True)

1

It would be fantastic to have a logic analyzer integrated into the language. Most logic analyzers seem to be bolted on and are quite cumbersome to use. Most basic use...

hansfbaier

Integrating design with bus.

4

I struggle to find an documentation or tutorial on how to integrate a design with the bus (such as AXI or Wishbone), and whether there is an option to automatically...

m-kru

Separate `Record` into `PackedStruct` and `Interface` components

5

`Record.connect` is very rarely useful, but _looks_ broadly useful. It should be deprecated (and ideally replaced with something better).

awygle

Currently, `ReadPort` and `WritePort` do not respect the clock polarity of the domain. This makes it impossible to use `Memory` with negedge domains. see: https://github.com/nmigen/nmigen/blob/d09dedfb485ee94cb492ef8e44ebb87260892532/nmigen/hdl/mem.py#L281 https://github.com/nmigen/nmigen/blob/d09dedfb485ee94cb492ef8e44ebb87260892532/nmigen/hdl/mem.py#L177

anuejn

`AssertionError` when running `Platform.build` with a `Module` using an `Instance`.

3

The following code snippet triggers an assertion failure: ```python from nmigen import * from nmigen_boards.tinyfpga_ax2 import * from nmigen.build import * from nmigen_boards.resources import * plat = TinyFPGAAX2Platform() plat.add_resources([Resource("led", 0,...

cr1901

Our recommended way to write testbenches is racy

4

We currently nudge people towards writing testbenches where the testbench modifies signals (inputs, registers) on the same edge as the edge-triggered synchronous logic (i.e. posedge for default posedge domains), but...

whitequark