yosys topic

Enigma in FPGA

mmicko

An abstraction library for interfacing EDA tools

olofk

draws an SVG schematic from a JSON netlist

nturley

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

The-OpenROAD-Project

CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR

cariboulabs

A modern hardware definition language and toolchain based on Python

amaranth-lang

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

m-labs

SystemVerilog to Verilog conversion

zachjs

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

efabless

A VHDL frontend for Yosys

forflo