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Published 20 hours ago • verified publisher icon amaranth-lang

Memory ReadPort and WritePort are broken for negedge clockdomains

Open anuejn opened this issue 4 years ago • 0 comments

Currently, ReadPort and WritePort do not respect the clock polarity of the domain. This makes it impossible to use Memory with negedge domains.

see: https://github.com/nmigen/nmigen/blob/d09dedfb485ee94cb492ef8e44ebb87260892532/nmigen/hdl/mem.py#L281 https://github.com/nmigen/nmigen/blob/d09dedfb485ee94cb492ef8e44ebb87260892532/nmigen/hdl/mem.py#L177

anuejn avatar May 18 '21 17:05 anuejn