Integrating design with bus.

[m-kru]

I struggle to find an documentation or tutorial on how to integrate a design with the bus (such as AXI or Wishbone), and whether there is an option to automatically generate status and control registers. I have found in https://github.com/m-labs/misoc README that there used to be some kind of "automatic CSR maps" but it also misses to point to the source.

Is it possible to automatically generate control/status registers with nmigen? If yes, is there any tutorial on how to do that?

[whitequark]

This is handled as a part of https://github.com/nmigen/nmigen-soc/. However, that repository contains only a partial implementation at the moment.

[m-kru]

@whitequark Looks like there has been no work for few months.

[whitequark]

There's been a pandemic.

[ydnatag]

How can we contribute to the project?