amaranth

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[WIP] Implement RFC 41: `lib.fixed`

16

## Overview - This is a staging ground for experimenting with the ergonomics of `lib.fixed` while the [associated RFC](https://github.com/amaranth-lang/rfcs/pull/41) is being worked on. It started as a fork of @zyp's...

vk2seb

Add a documentation URL alias that always points at the latest release

1

Amaranth documentation is currently only available under `https://amaranth-lang.org/docs/amaranth//` for releases or `https://amaranth-lang.org/docs/amaranth/latest/` for HEAD. It would be convenient to have an alias like `https://amaranth-lang.org/docs/amaranth/stable/` that always points at the latest...

zyp

- RFC PR: amaranth-lang/rfcs#76 - Documentation PR: N/A - CI configuration PR: N/A

zyp

- RFC PR: https://github.com/eigenform/rfcs/blob/main/text/0074-structured-vcd.md - Implementation PR: N/A

whitequark

Vivado transparent memory issue

1

Hello, (this is not directly an Amaranth issue, but I think it is worth noting / documenting here) When generating Verilog code from Amaranth, Vivado fails to recognize read ports...

piotro888

Running ```python from amaranth import * from amaranth.back.verilog import convert from amaranth.lib import stream from amaranth.lib.wiring import In, Component class A(Component): a: In(stream.Signature(1, always_valid=True)) def elaborate(self, _): m = Module()...

rroohhh

Couldn't assign the register value to output port.

5

Here is my code. May I know why the r_dac_en couldn't assign to output port o_dac_en? ```python def __init__(self): super().__init__({ # Output port 'o_dac_en': Out(1) }) # end def __init__...

clin15-logi

Simulation performance degradation on Amaranth 0.5.x

8

I'm in the process of updating the Coreblocks codebase to use Amaranth 0.5.x releases. Unfortunately, I discovered a severe simulation performance regression. The commit https://github.com/amaranth-lang/amaranth/commit/7870eb344b143dbc3b4f1a03b0a1e178196b8ef8 causes tests to run multiple...

tilk

Clock constraint on custom sync domain clock signal causes error during template rendering

3

Adding a clock constraint on a new clock domain called `sync` causes an error during Jinja template rendering. Taking away `platform.add_clock_constraint(cd_sync.clk, 100e6)` or renaming the domain makes the error go...

qookei

`Any{Seq,Const}` are not comparable to data structures

2

Something like this: ```python from amaranth.lib import data from amaranth import Signal, Module from amaranth.asserts import AnyConst class S(data.Struct): a: Signal() m = Module() any_const = AnyConst(S) signal = Signal(S)...

rroohhh