amaranth

amaranth copied to clipboard

Using ClockSignal in platform.add_clock_constraint

3

Currently one cannot use a `ClockSignal` in `platform.add_clock_constraint`: ```python3 from nmigen import * from nmigen_boards.microzed_z010 import * plat = MicroZedZ010Platform() plat.add_clock_constraint(ClockSignal(), 25e6) ``` fails with ``` Traceback (most recent call...

rroohhh

Can I create an active-low (asynchronous) reset?

13

Refiling here instead of other repo. Sorry if it's a duplicate. Specifically, I'm looking to mimic the following SystemVerilog code: ```systemverilog always_ff @(posedge clk, negedge rst_n) if (~rst_n) q

hofstee

Currently there's no support for generating the required files to synthesize for Polarfire FPGAs. I'm opening this issue to track progress towards completion as I work on this and to...

Lunaphied

Error accessing ResetSignal()

6

I want to toggle the reset signal of a module in simulation, but I get an error that do not quite understand. Here is a simple example: ```python from nmigen...

GuzTech

cxxsim: directly initializing memory

3

We currently use code similar to this, in PySim, to re-initialize the memory state in one go, before a sub-test: ```python from nmigen import Module, Memory from nmigen.sim import Simulator...

cestrauss

Way to start register with "random" value?

15

I'm guessing the answer is just going to be, run SymbiYosys in prove mode. But just in case I'm missing something... I would love to do something like this: ```python...

RobertBaruch

Python testbenches should not be able to assign combinatorially driven signals

2

Found this by accident, as I don't really have a use case for overriding driven signals. Nevertheless, pysim seems to allow this. Consider: ```python from nmigen import Signal, Module from...

cestrauss

Emit a diagnostic when parentheses are omitted in logical expressions with comparisons

8

E.g. `foo and bar == 0` is OK, but `foo & bar == 0` is parsed differently due to precedence, and virtually always results in a nasty bug. It's not...

whitequark

nMigen platforms are much more powerful than typical constraint files: apart from pin locations they also specify pin polarities, support indirect addressing through connectors, and in some cases include multiple...

whitequark

[RFC] Add InstanceResource to use Instance I/O as Platform I/O

8

This is an RFC for #308. Some chips like the Intel Cyclone V SoC and Xilinx Zynq require `Instance`s to access certain I/O functions not directly available through top-level module...

Ravenslofty