amaranth

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lib.fifo: fix reset handling of asynchronous FIFOs.

1

Asynchronous FIFOs do not properly handle a write domain reset (i.e. `w_level` is not reset to 0). This PR attempts to fix their behaviour.

jfng

vendor.lattice_machxo_2_3l: fix sdc generation

14

This PR fixes both issues reported in #546 . Probably there is a similiar issue for ecp5 and ice40 since they both use synplify.

anuejn

Individual Pin Inversion

8

This PR implements individual pin inversion as discussed in RFC #510. I was unsure about changing the internal representation of invert from a single bool to a tuple of bool....

anuejn

nmigen.sim._pyrtl: Add support for Assert/Assume

3

Fixes #427 TODO: * [ ] Ensure that I'm generating gen_test the right way * [ ] Improve the exception message? * [ ] Add unit tests * [ ]...

jeanthom

dsl: issue a warning if defining a case after the default

1

Resolves #404 Signed-off-by: Filipe Laíns

FFY00

sim: Add Observer

1

Adds an Observer interface to the simulator, allowing arbitrary code to receive values from the simulation. The implementation is based on the implementation of write_vcd. An obvious next step would...

alanvgreen

Order of bits within pattern syntax should be documented

2

For "pattern syntax" in `Case` and `Value.matches` it's not obvious where the least significant bit is in the pattern (first or last character in the string). It would be nice...

Ravenslofty

Time-0 race condition for simulation

6

**Minimal test case**. [simbug.zip](https://github.com/nmigen/nmigen/files/5961206/simbug.zip) **Summary:** The Verilog that nMigen outputs can contain time-0 race conditions which cause problems for simulation. **Details:** I'm running through the Zero to Asic course using...

RobertBaruch

Implement missing CXXRTL features

4

Integrating CXXSim requires a number of improvements to the Yosys CXXRTL backend that have to be done upstream. ## Remaining tasks See also https://github.com/nmigen/nmigen/issues/324 for nMigen-side view of these tasks....

whitequark

Add support for Print in simulation

6

A `Display` feature, similar to Verilog `$display`, has been requested a few times. We would depend on Yosys to implement it, which in fact is strongly in favor of having...

whitequark