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A modern hardware definition language and toolchain based on Python

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This RFC is a continuation of #381 . Currently, in order to change the shape of a signal, the following workarounds are needed: * for truncation, use `v[:new_width]` * for...

rfc

I have a board that has some inverted differential pairs broken out to a connector. The connector is used on several boards and there are daughterboards that can be plugged...

feature
platform:all
meta:needs-rfc

We currently do not have a way to define an explicit relationship between a clock and another user-generated clock, derived from the former. The relationship would be expressed in terms...

feature

Adding `Assert` support in pysim would be helpful for migrating LiteX code that relies on Display statements. While not equivalent to the Display statement, it would give enough information to...

feature
simulator:pysim
simulator:cxxsim

See https://github.com/nmigen/nmigen/issues/484#issuecomment-678810607.

feature

It would be useful to be able to indicate that a Switch should cover all possible Cases, or at least that the given Cases should not overlap.

feature
meta:needs-rfc

Right now, `Array` holds a special position in the language: it is one of the few constructs (the other being indexed part select) that encapsulates control flow, and at the...

feature
meta:needs-rfc

**Issue by [whitequark](https://github.com/whitequark)** _Sunday May 12, 2019 at 13:25 GMT_ _Originally opened as https://github.com/m-labs/nmigen/issues/66_ ---- An Array is essentially a mux, and there are several equally valid ways to drive...

feature

It appears that Yosys now supports `$divfloor` as of https://github.com/YosysHQ/yosys/commit/edd8ff2c0778d97808869488cc7394151456c4ca In `ast.py` it is mentioned that the different semantics mean it's not supported: https://github.com/nmigen/nmigen/blob/e46118dac0df315694b0fc6b9367d285a8fc12dd/nmigen/hdl/ast.py#L173-L179 I'm not sure what division synthesizes...

feature
upstream

```python from nmigen import * from nmigen_boards.ecpix5 import * class Top(Elaboratable): def elaborate(self, platform): m = Module() ddr3 = platform.request("ddr3", 0, dir={"arrosoir":"-"}, xdr={"chaise":4}) return m if __name__ == "__main__": top...

improvement