amaranth

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Simulation : abort simulation when step() does not converge

4

# Context Done with writing my code and running a simulation, the simulator is stuck in an infinite loop. After the last yield of the added sync process, `PySimEngine.step()` is...

sporniket

[RFC] add pre-run simulation hook for cli.main

1

as far as i can tell, current simulation cli-based workflow for a module is the following: module.py: ```python main(m, ...) ``` which gives control to cli.py: https://github.com/nmigen/nmigen/blob/746886ca8ac3b9a8941b540a347452805acbbcf2/nmigen/cli.py#L68-L73 which sets up...

github-4o

Elif without preceding If causes Syntax error when Elif has a complex condition

4

I'm getting a syntax error when using a function call that creates a signal inside an Elif. I can understand why this kind of function call might be problematic in...

alanvgreen

Cover `amaranth.build.dsl` with documentation

1

Starting to document the `amaranth.build` module and thought the DSL portion was a useful place to start since it's the most frequently encountered. Due to Git issues I accidentally forced...

Lunaphied

Guidance on naming - when to say "Amaranth HDL" versus just "Amaranth".

7

It would be useful to have some guidance on preferred usage of the project's new name. The full title of the project is now "Amaranth HDL", but in most instances...

martinling

It has (technically) been deprecated since day 1, and hasn't seen much uptake. This interface was considered important for migration of existing codebases, but the (intentional and unintentional) mismatches with...

whitequark

This interface has been deprecated for a while and is one of the ugliest remnants of Migen.

whitequark

Memory initializers are ignored when synthesizing with Diamond

2

The memories end up initialized to zero. Diamond complains: ``` @N:[CG364](https://github.com/amaranth-lang/amaranth/issues/@N:CG364:@XP_HELP) : [top.v(1686)](https://github.com/home/whitequark/Projects/luna/build/top.v:1686:7:1686:15:@N:CG364:@XP_MSG) | Synthesizing module U$$1$31 in library work. @W:[CG532](https://github.com/amaranth-lang/amaranth/issues/@W:CG532:@XP_HELP) : [top.v(1780)](https://github.com/home/whitequark/Projects/luna/build/top.v:1780:2:1780:9:@W:CG532:@XP_MSG) | Within an initial block, only Verilog...

whitequark

Currently the `AsyncFIFO` will continue to "read" entries from a FIFO that is held in `r_rst` (read reset) as long as `r_rdy` (read ready) is set. This behavior is undesirable...

Lunaphied

Support for PLL primitives

37

The goal of this issue is to document the kinds of PLL primitives of the various FPGA manufacturers, so that we can support them in nmigen. --- ## Lattice Lattice...

GuzTech