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Detect dual test case run

5

Fix #795 Prevent from calling twice the same test case. Reset the number of run tests when test_runner_setup is called. Add tests.

std-max

Using last item in stack using pop_stream

1

I have a question about finding the last item in a stream when using pop_stream. I am using pop_stream with a uart_slave for debugging an IP, I would like to...

basedVecna

--export-json without preprocessed path

7

I noticed a problem with the tool `vunit-test-explorer` (https://github.com/Bochlin/vunit-test-explorer/issues/17). Here you can jump from the GUI to the source code of the test case with one click, which is very...

timrid

Improving regexs that scan attributes

5

Fix #670

std-max

Support hierarchical library mapping in ModelSim

6

The library section of the modelsim.ini file allows to refer to a subordinate INI file using an "others" clause (subordinate files may also contain an "others" clause). The current implementation...

ThomasWismer

Error with large arrays and GHDL.

21

Hello, Im having problems with: ``` variable in_mod : integer_array_t; in_mod := load_csv("./input.csv",g_SIZE_MOD,true); ``` When **input.csv** is a large file GHDL crash without reason :S Thank you.

qarlosalberto

Drive invalid in AXI VCs

6

When the 'valid' signal is low for an AXI (-Lite) channel, the signals of the channel should be driven with 'X'. They should not keep their value from the last...

LukasVik

vhdl_parser.py: components should not be converted to lower-case while instantiating Verilog modules

10

I have a case where a VHDL entity (say vhdl_top) is instantiating a Verilog module with upper-case letters (say VERILOG_MODULE): VERILOG: ``` module VERILOG_MODULE ( ..... endmodule ``` The component...

krishnan-gopal

Feature Request: Allow to add *.gtkw files to a testbench for GTKWave

2

I want to store "GTKWave" save files along with my testbenches, so that I don't have to reconfigure the view all the time. This is possible by executing `run.py --gtkwave-args...

sudden6

VHDL 'package name' and 'file name' inconsistencies need to be fixed

6

Some package files under **https://github.com/VUnit/vunit/tree/master/vunit/vhdl/*** have inconsistencies in their package name and file name. So there is a need to modify the file names of such VHDL packages. The following...

dpaul24