Fixed AsyncFifo so reset not tied to 0

[da-steve101]

Previous logic was

if reset = 1
  s1_rst = 0
else
  s1_rst = reset // reset = 0

changed to

s1_rst = reset

[ghost]

Can one of the admins verify this patch?

[ucbjrl]

ok to test

[aswaterman]

That looks correct to me. However, I'm also wondering about the other Regs that are reset with init=. They appear to be using the module's implicit reset, which is probably incorrect for either the read side or the write side... right?

[sdtwigg]

No, assuming things haven't changed too much since I last peered into the recesses of chisel MCD code: If a register defines an explicit clock, then the reset signal attached to that clock is used to reset that register. AFAIK, nothing in that module uses the implicit reset.

I think, on a more philosophical level, if this AsyncFIFO is going to get some more exposure, its 'contract' (particular, reset behavior across clock domains) should be more explicitly explained spelled out. If I recall, this AsyncFIFO relies on higher-level reset synchronization between the clock domains. For example, you will get incorrect behavior if one side goes in and out of reset and the other side does not reset. Also, the module assumes that it is OK to use only 2 registers to construct a synchronizer between the two clock domains.