Move emitRef from Verilog to backend

[da-steve101]

Currently not passing the tests as for some test cases are named twice and hence index does not start at 0. Not sure where this is happening, but seems like it shouldn't be. Any suggestions on where to look?

[ucbjrl]

I've tried to incorporate these suggestions (and simplify naming - generate names once during nameAll()). Please check branch pr487.

[da-steve101]

I don't think T and C should have equivalence. Looking at src/test/resources/MultiClockSuite_Comp_1.v, this verilog is actually unsynthesizable as T0 is used for clock and temporary variable but passes the test.

[ucbjrl]

Good catch Steve. I'll revert the change to TextComparator and add the new output (replacing T0 with C0) as the "success" case (commits 040bb98, 16cf362).

[ucbjrl]

There is interaction between this change and multi-word literals in the C++ backend. I think we need to visit all clients of emitIndex and verify consistent usage (possibly forcing everyone to use Backend.emitRef).

[ghost]

Can one of the admins verify this patch?