Henrik Fegran

Can we change this to a draft PR until it is ready for proper review?

Thank you @eroom1966, That document seems to answer my questions. As for the systemverilog side of things, as the CLIC-parameters are statically defined at elaboration time, we should be able...

@Imperas Our stance, as previously communicated by @Silabs-ArjanB, is that the new interface is to be implemented and triaged within our testbench to the same quality standard, including regression status,...

I guess this is to some extent a matter of interpretation and to a certain degree organization; to me your reasoning appears sound, @MikeOpenHWGroup. Furthermore I don't think that there...

csr_access_test script (from riscv-dv) does not support our interpretation of WARL - all bits in WARL-defined register fields are assumed fully RW by the test generator. One example: write: 0x5a5a_5a5a...

> @Silabs-ArjanB > > for the issue mentioned here > > > mret in debug mode increments minstret ([openhwgroup/cv32e40x#558](https://github.com/openhwgroup/cv32e40x/issues/558)). > > Which cores does this apply to E40P, E40X, E40S...

> (0.2.0) Bitmanip enable-overrides appears to not function correctly (e.g. ctz triggers illegal instruction when enabled) > > can you please tell me how to reproduce this issue Thanks for...

> Hi @silabs-hfegran I now see this test passing with a minor adjustment to the configuration, we were simply missing the inclusion of .bitmanip_version = RVBV_1_0_0, // Bit Manipulation version...

Hi Lee, We are currently running all tests mentioned in core-v-verif/cv32e40x/regress/cv32e40x_full.yaml, any test not mentioned in that file or with a configuration that is not specified in that file are...

> @silabs-hfegran, this issue looks like it has gone stale. What is its status? @MikeOpenHWGroup, I am uncertain about the current status of this issue - perhaps @silabs-mateilga or @silabs-oysteink...